The present invention relates to scaling logic verification, and more specifically, to simplifying a netlist by identifying unate primary inputs.
Contemporary hardware designs are typically complex and include a diversity of different logic such as bit-level control logic, data paths of various types (e.g., including pipeline stages, queues, and RAM) with error identification logic, performance related artifacts (e.g., pipelining, multi-threading, out-of-order execution, and power saving techniques), and pervasive logic artifacts used to initialize the design, monitor its runtime execution, detect and cope with faults. While verifying hardware designs is necessary, the increased complexity of hardware designs has made verification more difficult. As such, techniques which reduce the size of the design being verified can make a large positive impact on the tractability of the verification task. These techniques can reduce the complexity of the logic design thereby reducing the risk of missing design flaws while reducing the time required to complete the design process.